There is a current interest in CMOS active pixel imagers for use as low cost imaging devices. An exemplary pixel circuit of a CMOS active pixel sensor (APS) is described below with reference to FIG. 1. Active pixel sensors can have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies, and promise higher readout rates compared to passive pixel sensors. The pixel circuit of FIG. 1, designated generally by reference number 100, includes an exemplary pixel cell 150, which is a 3T APS cell, where the 3T is commonly used in the art to designate use of three transistors to operate the pixel. The 3T pixel cell 150 includes a photodiode 162, reset transistor 184, source follower transistor 186, and a row select transistor 188. It should be understood that while FIG. 1 shows the circuitry for operation of a single pixel, in practical use there will be an M by N array of identical pixels arranged in rows and columns, with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
The photodiode 162 of the 3T pixel cell 150 converts incident photons to electrons which collect at node A. The source follower transistor 186 has its gate connected to node A and thus amplifies the signal appearing at node A. The signal amplified by transistor 186 is passed on a column line 170 to the readout circuitry when a particular row containing the cell 150 is selected by the row selection transistor 188. The photodiode 162 accumulates a photo-generated charge in a doped region of the substrate. It should be understood that the CMOS imager might include a photogate or other photoconversion device, in lieu of a photodiode, for producing photo-generated charge.
A reset voltage source Vrst is selectively coupled through reset transistor 184 to node A. The gate of the reset transistor 184 is coupled to a reset control line 191 which serves to control the reset operation (i.e., Vrst is connected to node A). Vrst may be Vdd. The row select control line 160 is coupled to all of the pixels of the same row of the array. Voltage source Vdd is coupled to a source follower transistor 186 and its output is selectively coupled to a column line 170 through the row select transistor 188. Although not shown in FIG. 1, the column line 170 is coupled to all of the pixels of the same column of the array and typically has a current load at its lower end. The gate of the row select transistor 188 is coupled to the row select control line 160.
As known in the art, a two step process is used to read a value from pixel 150. During a charge integration period, the photodiode 162 converts photons to electrons which collect at the node A. The charges at node A are amplified by source follower transistor 186 and selectively passed to the column line 170 by the row access transistor 188. During a reset period, node A is reset by turning on the reset transistor 184, such that the reset voltage Vrst is applied to node A and read out to the column line 170 by the source follower transistor 186 through the activated row select transistor 188. As a result, the two different values—the reset voltage Vrst and the image signal voltage Vsig—are readout from the pixel and sent by the column line 170 to the readout circuitry where each is sampled and held for further processing as known in the art.
All pixels in a row are read out simultaneously onto respective column lines 170 and the column lines are activated in sequence for reset and signal voltage read out. The rows of pixels are also read out in sequence onto the respective column lines.
FIG. 2 shows a CMOS active pixel sensor integrated circuit chip that includes a pixel array 230 and a controller 232 which provides timing and control signals to enable the reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M×N pixels, with the size of the array 230 depending on a particular application. The imager is read out a row at a time using a column parallel readout architecture. The controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240. Charge signals stored in the selected row of pixels are provided on the column lines 170 (FIG. 1) to a readout circuit 242 in the manner described above. The pixel signal read from each of the columns then can be read out sequentially using a column addressing circuit 244. The differential signal, Vdiff=(Vrst−Vsig), corresponds to the reset signal minus the integrated charge signal and is provided by the outputs Vout2, Vout1 of the readout circuit 242.
FIG. 3 more clearly shows the rows and columns 349 of pixels 350. Each column includes multiple rows of pixels 350. Signals from the pixels 350 in a particular column can be read out to a readout circuit 351 associated with that column. The read out circuit 351 includes sample and hold circuitry for acquiring the pixel reset (Vrst) and integrated charge signals (Vsig). Signals stored in the readout circuits 351 can be read sequentially, column-by-column, to an output stage 354 which is common to the entire array of pixels 330. The analog output signals can then be sent, for example, to a differential analog circuit and which subtracts the reset and integrated charge signals, (e.g., combines the two voltages and determines the difference between the circuits) and sends them to an analog-to-digital converter (ADC), or the reset and integrated charge signals are each supplied to the analog-to-digital converter.
FIG. 4 shows a sample and hold readout circuitry contained in column readout circuit 351. The FIG. 4 circuit samples and holds the Vsig and Vrst values for subsequent use by an output stage 354 (FIG. 3). For example, a Vsig from a desired pixel (“Vsig1”) coupled to a column line 470 is stored on capacitor 420 and a Vrst from the desired pixel (“Vrst1”) is stored on capacitor 418. Then the Vrst and Vsig signals for the desired pixel are readout to an output stage 354 (FIG. 3).
As seen in FIG. 4, the column line 470 is selectively coupled through SH_R switch 410 to the front side of capacitor 418. The backside of capacitor 418 is selectively coupled through switch 426 to a first input to output stage 354. The front side of capacitor 418 is also selectively coupled through crowbar 411, which includes a switch 413, to the front side of capacitor 420. The column line 470 is also selectively coupled through SH_S switch 412 to the front side of capacitor 420. The backside of capacitor 420 is selectively coupled through switch 428 to a second input to output stage 354. A clamp voltage Vcl (e.g., Vclamp) is selectively coupled to the backside of capacitor 418. Vcl (e.g., Vclamp) is selectively coupled through a switch 415 to the backside of capacitor 418. Vcl is also selectively coupled through another switch 417 to the backside of capacitor 420. A line voltage, e.g., a load voltage, Vln is selectively coupled through switch 436 and switch 410 to the front side of capacitor 418. A line voltage Vln is also selectively coupled through switch 436 and switch 412 to the front side of capacitor 420. The line voltage Vln is typically coupled to a current source for biasing the source follower transistor of the selected pixel.
The operation of the FIG. 4 circuit is now described with reference to the simplified signal timing diagram of FIG. 5 (assuming a readout from a 3T pixel). To store Vsig and Vrst from the desired pixel, a pulse signal CLAMP is applied which temporarily closes the switches 415, 417 and couples a Vclamp voltage to the back of the capacitors 418, 420 placing a charge on the respective back sides of respective capacitors. A pulse signal Vln_en is also applied which couples the desired pixel to a Vln voltage through the column line 470. To store Vsig on capacitor 420 while the pixel is in the signal sampling phase, a pulse signal SH_S is applied which temporarily closes the switch 412 and couples the desired pixel with the front side of capacitor 420 through the column line 470. Thus, Vsig is stored on capacitor 420. After the desired pixel is pulsed by a pixel reset signal, the pixel is in reset signal sampling phase. To store Vrst on capacitor 418 pulse signal SH_R is applied which temporarily closes the switch 410 and couples the desired pixel with the front side of capacitor 418 through the column line 470. Thus, Vrst is stored on capacitor 418.
To transfer Vsig and Vrst through the output stage 354 (FIG. 3), pulse signals COLSEL and CB, are applied which temporarily close switches 413, 426, and 428 and forces the signal stored on the back side of the respective capacitor 418, 420 through output stage 354. Thus, the amplified Vsig and Vrst signals are forced downstream to output stage 354.
One issue associated with the APS CMOS imaging systems is that of fixed pattern noise, which is type of distortion in the image captured by the imaging system. One source of fixed pattern noise is due to imperfections in the sample and hold circuit. The layout of the sample and hold circuit contributes to the amount of fixed pattern noise. In particular, the crowbar switch in the sample and hold circuit, i.e., 413 in FIG. 4, introduces a potential asymmetry in the cell with different coupling strengths among the sampling capacitor nodes. Due to the delta sampling nature of the timing scheme, floating capacitor plates are still present in the circuit with a direct coupling to each other and this presents a detrimental effect for any further improvement to the sensor fixed pattern noise. Additionally, the crowbar switch acts as a memory cell for the common mode voltage of the previously read-pixel belonging to the earlier row.
A sample and hold circuit having a reduced fixed pattern noise is desired.